Flash memories are becoming increasingly popular. However, some persistent drawbacks exist with conventional flash memories. For example, many conventional flash memories employ a large block erase limitation that is capable of erasing no less than a block of the memory at a time and re-programming the entire block with new data, even if only a small portion of the block needs to be re-programmed. Due to this relatively large re-programmning technique, conventional flash memories are slow to respond and cannot achieve a large number of erase/program cycles due to the stress on the memory cells inherent in the erasing and programming cycles.
One known flash memory has a limitation that it must erase the entire memory array or at least large block of approximately 64K bytes any time that a portion of memory needs to be re-programmed. A second known flash memory provides smaller page-erase feature that can typically erase and re-program 512 or 128 bytes at a time. Although the page-erase feature provides a smaller erase size, it still does not provide a high level of erase selectivity that is desired in order to promote fast operation and to reduce power consumption.
A second limitation of known flash memories is a low expected lifetime. Erasing and re-programming the memory stresses the transistors. Since known techniques erase and re-program large blocks of memory, all the transistors in the block are stressed. Over time, the stress reduces the flash memory life. For example, it is very difficult to build a flash memory that can survive 10 6 erase/program cycles due to the stress on a large block of memory every time any portion of the block needs to be modified. Therefore, a method of reducing stress in a flash memory is an important development.
A goal of the invention is to overcome the identified problems and to provide a new technique to select a flexible portion of memory to be erased. In an exemplary embodiment, the minimum erase size is a portion of a word (e.g. a byte). The invention provides that unnecessary erase/program cycles are not performed on the deselected cells. As a result, a the invention can provide a large number of operable erase/program cycles, such as 10 6 write/erase cycles, in a flash memory.